Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execution of a program, four data words P, Q, R, and S are accessed in that order 10 times (i.e., PQRSPQRS…). Hence, there are 40 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R, and S are 0xA248, 0xC28A, 0xCA8A, and 0xA262, respectively. For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?

Question

Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execution of a program, four data words P, Q, R, and S are accessed in that order 10 times (i.e., PQRSPQRS…). Hence, there are 40 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R, and S are 0xA248, 0xC28A, 0xCA8A, and 0xA262, respectively. For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?

Every access to S is a hit.
Once P is brought to the cache it is never evicted
At the end of the execution only R and S reside in the cache
Every access to R evicts Q from the cache

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AhmedNazir · Answer 1 · Sep 04, 2022 04:29:57

Option :

The correct answer is option 1, option 2, and option 4.

Concept:

The given data,

Cache Memory Size = 2 KB

Main Memory Size = 64 KB

Block Size = 64 B

Calculation:

Number of Lines =Cache Memory Size / Block Size

Number of Lines = 2K/ 64

Number of Lines = 2¹¹/2⁶

Number of Lines = 2⁵

16 bit

Tag

5 bit

Number of lines

5 bit

Word Offset

6 bit

The addresses of the first bytes of P, Q, R, and S are,

P	(A248)H	10100 01001 001000	9 th block
Q	(C284)H	11000 01010 000100	10 th block
R	(CA8A)H	11001 01010 001010	10 th block
S	(A262)H	10100 01001 100010	9 th block

But P&S are from the same memory block (10100).

Every access of S is hit.
Once P is brought to the cache it is never evicted.
Every access to R evicts Q from the cache.

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Hence the correct answer is option 1, option 2, and option 4.

1 Answers